Automatic Constraint Generation for Boundary Scan Interconnect Tests

Abstract

This paper discusses an algorithm to automate the generation of constraints files by leveraging a simple extension to the device characteristic model. This extension consists of additional pin-level restriction data that defines the test constraints. While additional constraints based on the unique features of the design may still be required, the component… (More)

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Cite this paper

@inproceedings{Baker2002AutomaticCG, title={Automatic Constraint Generation for Boundary Scan Interconnect Tests}, author={Kendrick Baker and Rick Borton}, year={2002} }