Automated formal verification of processors based on architectural models

@article{Khne2010AutomatedFV,
  title={Automated formal verification of processors based on architectural models},
  author={Ulrich K{\"u}hne and Sven Beyer and J{\"o}rg Bormann and John Barstow},
  journal={Formal Methods in Computer Aided Design},
  year={2010},
  pages={129-136}
}
To keep up with the growing complexity of digital systems, high level models are used in the design process. In today's processor design, a comprehensive tool chain can be built automatically from architectural or transaction level models, but disregarding formal verification. We present an approach to automatically generate a complete property suite from… CONTINUE READING