Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs

@article{Goud2013AtomisticTB,
  title={Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs},
  author={A. Arun Goud and Sumeet Kumar Gupta and Sri Harsha Choday and Kaushik Roy},
  journal={71st Device Research Conference},
  year={2013},
  pages={51-52}
}
The excellent control over short channel effects achievable using FinFETs have made them an attractive choice for realizing low-power and robust logic circuits and SRAMs in ultra-scaled technologies [1]. For deeply scaled gate lengths of the order of 5nm, increased direct source to drain tunneling (DSDT) is expected to contribute significantly to the off-state leakage current [2]. Gate underlap has been previously investigated as an effective way to reduce the thermionic component of leakage… CONTINUE READING
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