At-Speed SEE Testing of RHBD Embedded SRAMs

  title={At-Speed SEE Testing of RHBD Embedded SRAMs},
  author={E. Cannon and J. Tostenrude and M. Caba{\~n}as-Holmen and B. Meaker and Charles Neathery and Michael Carson and R. Brees},
  journal={IEEE Transactions on Nuclear Science},
We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell Upsets (MCU), Multiple Bit Upsets (MBU), persistent errors and transient errors. Error Detection and Correction (EDAC) can reduce the residual error rate due to SEU by multiple orders of magnitude. Consequently, careful testing of the at-speed test structure is essential to detect and quantify the risk of… Expand
Multiple Cell Upset Classification in Commercial SRAMs
Estimating SEE Error Rates for Complex SoCs With ASERT
Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing
A method for efficient Radiation Hardening of multicore processors


Evaluating Alpha-induced soft errors in embedded microprocessors
Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM
Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)
SRAM SER in 90, 130 and 180 nm bulk and SOI technologies
Single Event Transients in Digital CMOS—A Review
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction
Heavy Ion, High-Energy, and Low-Energy Proton SEE Sensitivity of 90-nm RHBD SRAMs
Implementing Realistic Heavy Ion Tracks in a SEE Prediction Tool: Comparison Between Different Approaches
Measurement and reporting of alpha particle and terrestrial cosmic rayinduced soft errors in semiconductor devices
  • JEDEC Standard JESD
  • 2006