At-Speed SEE Testing of RHBD Embedded SRAMs

@article{Cannon2013AtSpeedST,
  title={At-Speed SEE Testing of RHBD Embedded SRAMs},
  author={Ethan H. Cannon and Joseph Tostenrude and Manuel Caba{\~n}as-Holmen and Barry Meaker and Charles Neathery and Michael Carson and Roger Brees},
  journal={IEEE Transactions on Nuclear Science},
  year={2013},
  volume={60},
  pages={4207-4213}
}
We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell Upsets (MCU), Multiple Bit Upsets (MBU), persistent errors and transient errors. Error Detection and Correction (EDAC) can reduce the residual error rate due to SEU by multiple orders of magnitude. Consequently, careful testing of the at-speed test structure is essential to detect and quantify the risk of… 
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References

SHOWING 1-9 OF 9 REFERENCES
Evaluating Alpha-induced soft errors in embedded microprocessors
TLDR
Cross sections for the different memory resources are reported as well as the error rate for different codes implemented as test benchmarks to find the contribution of each available resource to the overall device error rate.
Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM
TLDR
For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of theseMBU events.
Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)
TLDR
A generally applicable self test circuit approach implemented in IBM's 5AM SiGe process is demonstrated, and its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s is described.
Single Event Transients in Digital CMOS—A Review
The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moore's
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction
TLDR
Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing, and impacts on characterizing these effects in models and ground-based testing are presented, show that full circuit prediction is not yet well understood.
Heavy Ion, High-Energy, and Low-Energy Proton SEE Sensitivity of 90-nm RHBD SRAMs
We measure the sensitivity of different 90-nm SRAM cells to single-event upsets (SEUs) caused by heavy ions, high energy protons, and low energy protons. We discuss radiation hardened by design
Implementing Realistic Heavy Ion Tracks in a SEE Prediction Tool: Comparison Between Different Approaches
TLDR
A “refined average” approach is identified as a good trade-off for implementation in an engineer SEE prediction tool, taking into account sufficiently detailed physics, without asking for too much computer resources.
SRAM SER in 90, 130 and 180 nm bulk and SOI technologies
We investigate the soft error rate (SER) of bulk and SOI SRAMs at the 90, 130 and 180 nm technology nodes. We use accelerated testing and Monte Carlo modeling to determine SER sensitivity to
Measurement and reporting of alpha particle and terrestrial cosmic rayinduced soft errors in semiconductor devices
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