Asynchronous Design—Part 2: Systems and Methodologies
@article{Nowick2015AsynchronousD2, title={Asynchronous Design—Part 2: Systems and Methodologies}, author={Steven M. Nowick and Montek Singh}, journal={IEEE Design \& Test}, year={2015}, volume={32}, pages={19-28} }
This two-part article aims to provide both a short historical and technical overview of asynchronous design, as well as a snapshot of the state of the art. Part 1 covered foundations of asynchronous design, and highlighted recent applications, including commercial advances and use in emerging application areas. Part 2 focuses on methodologies for designing asynchronous systems, including basics of hazards, synthesis and optimization methods for both logic-level and high-level synthesis, and the…
28 Citations
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools
- Computer Science2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
- 2018
There is significant value in enabling users to verify asynchronous circuits using tools that may be more familiar, trusted or more widely adopted, and performance and verification capabilities against two verification tools for asynchronous circuits are compared.
VHDLASYN: A tool for synthesis of asynchronous systems from of VHDL behavioral specifications
- Computer Science2018 2nd Conference on PhD Research in Microelectronics and Electronics Latin America (PRIME-LA)
- 2018
The VHDLSYN tool synthesized a set of known benchmarks and implemented in the FPGA platform showing a high robustness to the mapping, i.e., free-hazard design.
Comparison of performance between synchronous and asynchronous processors A thesis submitted in partial fulfilment of the requirement for the award of the degree of MASTER OF TECHNOLOGY in VLSI Design
- Computer Science
- 2018
This thesis focuses on comparing the performance of synchronous processor and asynchronous processor and the time required for computation for both methodologies to prove effectiveness of asynchronous methodology over synchronous methodology.
An Open-Source EDA Flow for Asynchronous Logic
- Computer ScienceIEEE Design & Test
- 2021
This article presents an open-source EDA flow for digital asynchronous circuits, capable of supporting many different families of asynchronous circuit families from logic synthesis all the way down to GDSII.
Development flow of on-line Software Test Libraries for asynchronous processor cores
- Computer Science2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)
- 2018
A methodology for the validation of Software Test Libraries (STLs) targeting on-line testing of asynchronous processor cores is proposed, based exclusively on commercial tools, currently used in industry for functional safety analysis.
Null convention logic (NCL) based asynchronous design — fundamentals and recent advances
- Computer Science2017 International Conference on Recent Advances in Signal Processing, Telecommunications & Computing (SigTelCom)
- 2017
This paper presents a comprehensive introduction to the NCL design approach, from fundamentals to recent advances, and automated design flows for NCL circuits are also discussed.
Asynchronous Arbitration. Synthesis of Multi-input Asynchronous Arbiter with Consecutive Connection of Input Signals
- Computer ScienceCompSysTech
- 2021
A new solution is presented, which implements an order of asynchronous arbitration based on the understanding of the competition of service requests over time, and a specification for the synthesis of a metastable element and as a result of a fast two-input arbiter is formulated.
Invited: Advances in formal methods for the design of analog/mixed-signal systems
- Computer Science2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)
- 2017
An overview of the state-of-the-art in AMS formal verification and asynchronous design that enables the development of analog/asynchronous co-design methods, exemplified by the LEMA-Workcraft workflow currently under development by the authors.
Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited
- Computer ScienceDAC
- 2017
An overview of the state-of-the-art in AMS formal verification and asynchronous design that enables the development of analog/asynchronous co-design methods, exemplified by the LEMA-Workcraft workflow currently under development by the authors.
Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC
- Computer ScienceElectronics
- 2021
The double-layer energy efficient synchronous-asynchronous circuit-switched NoC (CS-NoC) is proposed to enhance the power utilization and reduces the overall power consumption by 23% when compared with recent previous work.
References
SHOWING 1-10 OF 54 REFERENCES
Proteus: An ASIC Flow for GHz Asynchronous Designs
- Computer ScienceIEEE Design & Test of Computers
- 2011
This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.
High-level asynchronous system design using the ACK framework
- Computer ScienceProceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
- 2000
ACK is a framework for designing high-performance asynchronous systems of this type that begins with procedural level descriptions of-control and datapath and results in a hybrid system that mires a variety of hardware implementation styles including burst-mode AFSMs, macromodule circuits, and programmable control.
Asynchronous design using commercial HDL synthesis tools
- Computer ScienceProceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)
- 2000
The paper considers a particular subclass of asynchronous circuits (Null Convention Logic or NCL) and suggests a design flow which is completely based on commercial CAD tools and argues about the trade-off between the simplicity of design flow and the quality of obtained implementations.
Synthesis of asynchronous state machines using a local clock
- Computer Science[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors
- 1991
A novel, correct design methodology for asynchronous state-machine controllers is presented, which allows multiple input changes which can arrive at arbitrary times and allows arbitrary state encoding and flexibility in logic minimization and gate-level realization, so it can take advantage of systematic CAD optimization techniques.
Relative timing [asynchronous design]
- Computer Science, PhysicsIEEE Trans. Very Large Scale Integr. Syst.
- 2003
Relative timing (RT) is introduced as a method for asynchronous design and enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases.
Balsa: An Asynchronous Hardware Synthesis Language
- Computer ScienceComput. J.
- 2002
This paper introduces Balsa, a language and framework for synthesizing circuits using a technique of syntax direct translation and introduces the key features of the language.
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
- Computer ScienceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 2006
This paper proves the feasibility and effectiveness of the proposed approach to desynchronization by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.
TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model
- Computer ScienceProceedings International Conference on Computer Design VLSI in Computers and Processors
- 1997
A new delay model, the scalable-delay-insensitive (SDI) model, is proposed for dependable and high-performance asynchronous VLSI system design and presented the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000.
Advances in asynchronous logic: From principles to GALS & NoC, recent industry applications, and commercial CAD tools
- Computer Science2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)
- 2013
This tutorial will cover the basic principles and advantages of asynchronous logic, some insights on new research challenges, and will present the GALS scheme as an intermediate design style with recent results in asynchronous Network-on-Chip for future Many Core architectures.
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
- Engineering2014 20th IEEE International Symposium on Asynchronous Circuits and Systems
- 2014
This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase quasi delay-insensitive circuits using Null Convention Logic.