Asymptotic waveform evaluation for timing analysis

@article{Pileggi1990AsymptoticWE,
  title={Asymptotic waveform evaluation for timing analysis},
  author={Lawrence T. Pileggi and Ronald A. Rohrer},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={1990},
  volume={9},
  pages={352-366}
}
For digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For mid-frequency MOS integrated circuits the RC tree methods can predict the delay to within 10 percent of a SPICE simulation and at faster than lOOOx the speed. With continual progress in integrated circuit processing… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 17 references

RC trees revisited,

  • M. A. Cirit
  • Proc. Custom Integrated Circuits Conf.,
  • 1988

Dr Rohrer was the Pre\ident ot the IEEE Circuits and Sy\tenl\ Society

  • C Shi, K. Zhang
  • He has received \everdl engineering awards and in…
  • 1987

SPECS2: An integrated circuit timing simulator,

  • C. Visweswariah, R. A. Rohrer
  • in Proc. Int. Con5 on Computer-Aided Design,
  • 1987

TALISMAN: A piecewise linear simulator based on tree/link repartitioning,

  • H. Xiaoli, L. T . Pillage, R. A. Rohrer
  • in Proc. Int. Conf. on Computer-Aided Design,
  • 1987
1 Excerpt

Treeilink partitioning for the implicit solution of circuits,

  • L. T. Pillage, H. Xiaoli, R. A. Rohrer
  • in Proc. Int. Symp. on Circuits and Systems,
  • 1987
1 Excerpt

Signal delay in ECL interconnect,

  • IO P O’Brien, J Wyatt
  • Proc IEEE Int. Symp on Circuits and Svstems,
  • 1986

Signal delays in RC trees trical and computer engineering at Cdrnegie Mellon University. Pittsburgh. with charge sharing and leakage,

  • A Raghunathan, C D Thompson
  • Proc 19th Asilomur Conf on PA Circuit\. Svstems…
  • 1985

Ousterhout

  • . KJ
  • “CRYSTAL: A timing analyzer for NMOS VLSI…
  • 1983

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