Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

@article{Chaware2012AssemblyAR,
  title={Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer},
  author={Raghunandan Chaware and Kumar Nagarajan and Suresh Ramalingam},
  journal={2012 IEEE 62nd Electronic Components and Technology Conference},
  year={2012},
  pages={279-283}
}
For the last few decades semiconductor industry has been following Moore Law effectively, which has resulted in significant miniaturization of transistors and on chip logic circuitry. Below the 28nm node, as design complexity of the IC (Integrated Circuits) increases, cost and risk associated with these designs are becoming prohibitive for many companies. Three dimensions (3D) die stacking methodology offers unique advantages of low power and high bandwidth per watt without increasing the cost… CONTINUE READING
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