Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film

@article{Kao2012AssemblyAR,
  title={Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film},
  author={K. S. Kao and Ren-Shin Cheng and Chau-Jie Zhan and Jing-Yao Chang and Tsung-Fu Yang and Shin-Yi Huang and Chia-Wen Fan and Su-Mei Chen and Su-Ching Chung and Yu-lan Lu and Mei-Lun Wu and Tai-Hung Chen},
  journal={2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)},
  year={2012},
  pages={307-310}
}
In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips. For the multi-chip stacking with fine gap and fine pitch solder micro bump interconnection… CONTINUE READING