Armada: timing-driven pipeline-aware routing for FPGAs

  title={Armada: timing-driven pipeline-aware routing for FPGAs},
  author={Ken Eguro and S. Hauck},
  booktitle={FPGA '06},
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups have attempted to address this by developing new architectures that include registered switchpoints within their interconnect. Unfortunately, this pipelined communication presents a new and difficult problem for detailed routing tools. Known as the N-Delay Routing Problem, it has been proven to be NP-Complete. Although… Expand
19 Citations
Revision of 3042 1 Enhancing Routing Heuristics on Pipelined-FPGAs
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