# Arithmetic with binary-encoded balanced ternary numbers

@article{Parhami2013ArithmeticWB, title={Arithmetic with binary-encoded balanced ternary numbers}, author={Behrooz Parhami and Michael McKeown}, journal={2013 Asilomar Conference on Signals, Systems and Computers}, year={2013}, pages={1130-1133} }

Ternary number representation and arithmetic, based on the radix-3 digit set {-1, 0, ;1}, has been studied at various times in the history of digital computing. Some such studies concluded that we should abandon ternary in favor of binary computation. Others, demonstrated promise and potential advantages, but, for various reasons, including inertia, did not lead to widespread use. By proposing an efficient binary encoding for balanced ternary numbers, along with the corresponding arithmetic…

## 17 Citations

### Title Truncated ternary multipliers Permalink

- Computer Science
- 2015

An additional advantage is shown: that of lower-error truncated multiplication with the same relative cost reduction as in truncated binary multipliers.

### Truncated ternary multipliers

- Computer ScienceIET Comput. Digit. Tech.
- 2015

An additional advantage is shown: that of lower-error truncated multiplication with the same relative cost reduction as in truncated binary multipliers.

### Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units

- Computer ScienceArXiv
- 2019

Investigations show that none of the mentioned arithmetic units require a complete ternary full adder, and instead, they can be designed by use of partial ternARY fullAdder, whose input carry never becomes '2'.

### A programmable ternary CPU using hybrid CMOS/memristor circuits

- Computer ScienceInt. J. Parallel Emergent Distributed Syst.
- 2018

An implementation of a general purpose CPU using signed-digit arithmetic by exploiting memristors in order to implement multi-value registers is proposed and it is shown that a break-even point exists at which signed- digit algorithms outperform conventional binary arithmetic operations.

### On-line Digit Set Conversion for Rational Digit Number

- Computer Science
- 2017

This paper proposes a rational digit number system which is composed of rational signed-digits in the digit set and shows that this new system preserves a roundto-nearest property and is suitable for an on-line arithmetic computation.

### Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

- Computer ScienceSN Applied Sciences
- 2020

The proposed algorithm reduces the number of adders with large bit-width and the dependencies between consecutively process blocks, and the reverse converter architecture improves the delay and area on the FPGA Virtex Ultrascale + family platform in 14 nm/16 nm FinFET technology as compared to the related works.

### Partial Ternary Full Adder versus Complete Ternary Full Adder

- Computer Science2020 International Conference on Electrical, Communication, and Computer Engineering (ICECCE)
- 2020

Investigations show that none of these arithmetic units require a complete ternary full adder, and they can be designed by means of partial ternaries full adders, whose input carry never becomes ‘2’.

### N-digits Ternary Carry Lookahead Adder Design

- Computer Science2019 31st International Conference on Microelectronics (ICM)
- 2019

Two design approaches for N-digits ternary logic CLA based on K-map and threshold logic methods are proposed in addtion to their realization using CNTFETs only and memristor with CNTFets.

### Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology

- Computer ScienceMicroelectron. J.
- 2019

### Balanced Number System

- Computer ScienceResonance
- 2018

The article explores the application of binary and ternary number systems to three classical mathematical puzzles–weight problem of Bachet de Méziriac, binary numbers magic trick, and the detection…

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