Area minimization algorithm for parallel prefix adders under bitwise delay constraints

@inproceedings{Matsunaga2007AreaMA,
  title={Area minimization algorithm for parallel prefix adders under bitwise delay constraints},
  author={Taeko Matsunaga and Yusuke Matsunaga},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2007}
}
This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. This problem is treated as synthesis of prefix graphs which represent global structures of parallel prefix adders, and a two-folded robust heuristic is proposed. The first process is dynamic programming based area minimization (DPAM), where the search space is limited to a specific subset of the whole set of prefix graphs by imposing some restrictions on structure of prefix… CONTINUE READING
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