Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

Abstract

The Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3, 13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much… (More)
DOI: 10.2478/s13537-012-0006-8

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Cite this paper

@article{Khan2012AreaefficientPA, title={Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip}, author={Mohammad Ayoub Khan and Abdul Quaiyum Ansari}, journal={Central European Journal of Computer Science}, year={2012}, volume={2}, pages={76-85} }