Area efficient phase calibration of a 1.6 GHz multiphase DLL

@article{Agrawal2011AreaEP,
  title={Area efficient phase calibration of a 1.6 GHz multiphase DLL},
  author={Ankur Agrawal and Pavan Kumar Hanumolu and Gu-Yeon Wei},
  journal={2011 IEEE Custom Integrated Circuits Conference (CICC)},
  year={2011},
  pages={1-4}
}
This paper describes a digital calibration scheme that corrects for phase spacing errors in a multiphase clock generating delay-locked loop (DLL). The calibration scheme employs sub-sampling using a frequency-offset clock with respect to the DLL reference clock, to measure phase-offsets. The phase-correction circuit uses one digital-to-analog converter across eight variable-delay buffers to reduce the area consumption by 62%. The test-chip, designed in a 130nm CMOS process, demonstrates a 8… CONTINUE READING

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