Area efficient, low power and robust design for add-compare-select units

  title={Area efficient, low power and robust design for add-compare-select units},
  author={Mohammad Kazem Akbari and Ali Jahanian and Mohsen Naderi and Bahman Javadi},
  journal={Euromicro Symposium on Digital System Design, 2004. DSD 2004.},
This paper presents an area efficient, low-power and robust ACS unit for Viterbi decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon quasi delay insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the… CONTINUE READING
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