Area efficient, low power and robust design for add-compare-select units

@article{Akbari2004AreaEL,
  title={Area efficient, low power and robust design for add-compare-select units},
  author={Mohammad Kazem Akbari and Ali Jahanian and Mohsen Naderi and Bahman Javadi},
  journal={Euromicro Symposium on Digital System Design, 2004. DSD 2004.},
  year={2004},
  pages={611-614}
}
This paper presents an area efficient, low-power and robust ACS unit for Viterbi decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon quasi delay insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the… CONTINUE READING
5 Citations
10 References
Similar Papers

References

Publications referenced by this paper.
Showing 1-10 of 10 references

Fruber, “A Low-Power Self-Timed Viterbi Decoder

  • P. A. Riocereux, E. M. Brackenbury, M. Cumpstey, S.B
  • in Proc. 7 International Symp. on Asynchronous…
  • 2001
2 Excerpts

Power Reduction Techniques for a Viterbi Decoder Implementation

  • I. Bogdan, M. Mumunteanu, P. A. Ivey, N. L. Seed, N. Powell
  • ESPLD
  • 2000
3 Excerpts

Asynchronous Data paths and the Design of an Asynchronous Adder

  • A. J. Martin
  • Formal Methods in System Design,
  • 1992
2 Excerpts

Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits

  • A. J. Martin
  • UT Year of Programming Institute on Concurrent…
  • 1989
2 Excerpts

Similar Papers

Loading similar papers…