Corpus ID: 15033254

Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier

@inproceedings{Karunakaran2011AreaAP,
  title={Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier},
  author={S. Karunakaran},
  year={2011}
}

S. Karunakaran

Published 2011

Engineering

The FIR filter is commonly used in many applications such as communication or multimedia signal processing. In the existing method, the design of FIR filter structure, based on synchronous multiplier such as Wallace tree multiplier design is considered. It leads to fewer throughputs and increase in hardware complexity but there is considerable decrease in power consumption. This paper is focused on the design of an efficient VLSI architecture for asynchronous multiplier based FIR filter design… CONTINUE READING

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