• Corpus ID: 15033254

Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier

@inproceedings{Karunakaran2011AreaAP,
  title={Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier},
  author={S. Karunakaran},
  year={2011}
}
The FIR filter is commonly used in many applications such as communication or multimedia signal processing. In the existing method, the design of FIR filter structure, based on synchronous multiplier such as Wallace tree multiplier design is considered. It leads to fewer throughputs and increase in hardware complexity but there is considerable decrease in power consumption. This paper is focused on the design of an efficient VLSI architecture for asynchronous multiplier based FIR filter design… 
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6 Citations
Highly Influential Citations
1
Background Citations
3
Methods Citations
2

6 Citations

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters

TLDR
A Heterogeneous architecture, which composed of four different sub adders to design an adder unit is proposed in order to demonstrate trade-offs between performance parameters i.e. Area, Power and speed.

Performance of FIR Filter with Wallace Multiplier over FIR filter with Truncated Multiplier

TLDR
An efficient verilog HDL has been written, successfully simulated and synthesized in Xilinx and the results shows that proposed design achieves the best delay and power than existing system which uses the concept of truncated multiplier.

An asynchronous short word length Delta-Sigma FIR filter for low power DSP

TLDR
This work explores whether the highly pipelined organization of SWL systems can be exploited to produce usable ultra-low-power asynchronous DSP applications and shows that the filtering performance required by the applications requiring low power such as speech filtering applications can be obtained using ultra low supply SWL NCL operated down to 400mV.

An algorithm to improve the performance of medical signal filter with implementation using arm processor

TLDR
Handling the signal processing activities on an ARM Cortex M4 in its place of employing another difficult Digital Signal Processor has the understandable benefit that an additional processor is not essential, which results in optimized performance in the realized Digital filter.

PERFORMANCE ANALYSIS OF FIR FILTER BASED ON MULTIPLE CONSTANT MULTIPLICATION TECHINIQUE WITH EFFICIENT MULTIPLIER

TLDR
An efficient verilog HDL has been written, successfully simulated and synthesized in Xilinx and the results shows that proposed designs achieve the best area and power than existing system which uses the concept of truncated multiplier.

Estimation of Speed and Area of High Speed Multiplier Designed using Booth-Wallace Unit Add Method

TLDR
This paper presented the efficient implementation of high speed multiplier using Array, Booth, Booth - Wallace (16 bit) method and the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter.

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