Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier
@inproceedings{Karunakaran2011AreaAP, title={Area and Power Efficient VLSI Architecture for FIR Filter using Asynchronous Multiplier}, author={S. Karunakaran}, year={2011} }
The FIR filter is commonly used in many applications such as communication or multimedia signal processing. In the existing method, the design of FIR filter structure, based on synchronous multiplier such as Wallace tree multiplier design is considered. It leads to fewer throughputs and increase in hardware complexity but there is considerable decrease in power consumption. This paper is focused on the design of an efficient VLSI architecture for asynchronous multiplier based FIR filter design… CONTINUE READING
Figures and Tables from this paper
6 Citations
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters
- Computer Science
- 2014
- PDF
Estimation of Speed and Area of High Speed Multiplier Designed using Booth-Wallace Unit Add Method
- Mathematics
- 2013
- 1
- PDF
Performance of FIR Filter with Wallace Multiplier over FIR filter with Truncated Multiplier
- Engineering
- 2014
- 7
- Highly Influenced
- PDF
An asynchronous short word length Delta-Sigma FIR filter for low power DSP
- Computer Science
- 2016 10th International Conference on Signal Processing and Communication Systems (ICSPCS)
- 2016
References
SHOWING 1-10 OF 17 REFERENCES
Design of efficient multiplierless FIR filters
- Mathematics, Computer Science
- IET Circuits Devices Syst.
- 2007
- 26
- PDF
A high-speed, programmable, CSD coefficient FIR filter
- Computer Science
- IEEE Trans. Consumer Electron.
- 2002
- 68
- PDF
A Novel VLSI Divide and Conquer Implementation of the Iterative Array Multiplier
- Computer Science
- Fourth International Conference on Information Technology (ITNG'07)
- 2007
- 2
A Low-Voltage Micropower Asynchronous Multiplier With Shift–Add Multiplication Approach
- Mathematics, Computer Science
- IEEE Transactions on Circuits and Systems I: Regular Papers
- 2009
- 20
A high-speed, programmable, CSD coefficient FIR filter
- Computer Science
- ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)
- 2001
- 11
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors
- Computer Science
- IEEE Journal of Solid-State Circuits
- 2007
- 52
FIR Variable Digital Filter With Signed Power-of-Two Coefficients
- Mathematics, Computer Science
- IEEE Transactions on Circuits and Systems I: Regular Papers
- 2007
- 30
- PDF
Low-power differential coefficients-based FIR filters using hardware-optimised multipliers
- Mathematics, Computer Science
- IET Circuits Devices Syst.
- 2007
- 9
A micropower low-voltage multiplier with reduced spurious switching
- Engineering, Computer Science
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2005
- 55