- Published 1984 in Inf. Process. Lett.

The square n x n mat r ix mul t ip l ica t ion p rob l em in VLSI models has been inves t iga ted by several au thors [1-5]. Both the lower and the upper bounds to the t radeoff A T 2 between chip area A and c o m p u t a t i o n t ime T are of o rder n 4. Savage [1] has shown that the des igner of any circui t for mul t ip ly ing an m X n mat r ix by an n x p mat r ix ((in, rl, p) p rob lem) is conf ron ted with an a rea t ime t radeoff expressed by A T 2 = ~ ( m Z p 2 ) , when ( a n ) ( b n ) < 1⁄2n 2 with a = max(m, n) and b = max(n, p). N o lower b o u n d is known for the p rob l em (m, n, p) when ( a n ) x (b n) >~ 1⁄2n 2. In this pape r the result given in [1] is pa r t i a l ly e m ended and a new lower b o u n d is given which holds for any choice of m, n, p, with m >~ n, p >~ n. A s imilar lower b o u n d is con ta ined in an unpubl ished repor t [9] which was b rought to the a t tent ion of the au thor dur ing the refereeing process of this paper . The designs of Kung and Leiseron [4] for the (m, n, p) p r o b l e m yield an upper b o u n d which meets the lower b o u n d for m, p = ® (n). The th ree-d imens iona l m X n × p mesh of trees M(3, m, n, p) for the (m, n, p) p rob l em produces an u p p e r b o u n d which is op t ima l to within logar i thmic factors when max(m, p ) = O (n) or when bo th condi t ions n = O(m) and m = ®(p) hold. In the fol lowing we use the VLSI model introduced by Brent and Kung [6]. Deno te by two b ina ry matr ices E l and E 2 a par t i t i on of the e lements of a mat r ix E into two dis jo int sets, where each nonzero entry ident if ies an e lement in to the co r respond ing set. Given two b ina ry matr ices H ' and H" of the same size, the b ina ry matr ix ob ta ined by componen twise app ly ing the logical opera t ion op is deno ted by H ' op H"; ]H I is the number of nonzero entr ies in H. Cons ider the p rob l e m (m, n, p) of mul t ip ly ing an m x n mat r ix B by an n x p matr ix C, D being the resul t ing matr ix. Let M be the m a x i m u m number of the mp ou tpu t var iables genera ted together any por t of the mul t ip l ie r chip. By sl iding a line pe rpend icu la r to a d iamete r of the chip, the ou tpu t nodes can be d iv ided into two dis jo int sets, which co r respond to a pa r t i t ion D 1, D 2 of the mp ou tpu t var iables so that

@article{Lotti1984AreaTimeTF,
title={Area-Time Tradeoff for Rectangular Matrix Multiplication in VLSI Models},
author={Grazia Lotti},
journal={Inf. Process. Lett.},
year={1984},
volume={19},
pages={95-98}
}