Corpus ID: 17208258

Area Optimization of FIR Filter and its Implementation on FPGA

  title={Area Optimization of FIR Filter and its Implementation on FPGA},
  author={Vijender Saini and Balwinder Singh and Rekha Devi and Dept . Ece},
Digital Signal Processing is omnipresent in the modern world. Filtering is most important operation of Digital Signal Processing. FIR digital filters are widely used in DSP by the virtue of its stability, linear phase, fewer finite precision error and efficient implementation. First Low pass FIR Filter is designed by choosing CSD algorithms and MATLAB FDA Tool is used Coefficients calculation. The CSD numbers has the minimum number of non-zero digits and no consecutive nonzero digits. Now the… Expand
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Reconfigurable architecture for FIR filter with low power consumption
  • N. Jayasudha, K. Sathiya
  • Computer Science
  • 2013 International Conference on Information Communication and Embedded Systems (ICICES)
  • 2013
Low power reconfigurable architectural approach for finite impulse response(FIR) filter dynamically changes the filter order to achieve dynamic power savings with minor degradation in performance. Expand
FPGA Hardware Resource Specific Optimal Design for FIR Filters
F FIR filters with different techniques are implemented and the resource utilization of these different algorithms are compared using Virtex 6 FPGA and the time efficient technique is presented. Expand
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If the common adders and subtractors were computed for all filter coefficients that specified in CSD representation, it would significantly reduce the complexity of the hardware implementation of digital FIR filter. Expand
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Canonical signed digit representation for FIR digital filters
An example filter design is presented that shows the error involved in limiting the number of allowable non-zero CSD coefficients for a real FIR bandpass filter. Expand
Efficient Multiplication and Division Using MSP430
  • 2006
Multiplication and division in the absence of a hardware multiplier require many instruction cycles, especially in C. This report discusses a method that does not need a hardware multiplier and canExpand
Efficient FIR filter architectures suitable for FPGA implementation
This paper describes efficient architectures for FIR filters that allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA). Expand
Halonen,”Multiplier and shift using signed digit representations
  • Patent No. US 7,257,609 B1, Date of Patent: Aug
  • 2007
Multiplier and shift using signed digit representations
  • Multiplier and shift using signed digit representations
  • 2007
Multiplier and shift using signed digit representations ” Patent No
  • 2007
Reconfigurable FIR Filter using CSD Coefficients
  • United State, Patent No. US 7,164,712,
  • 2007
Reconfigurable FIR Filter using CSD Coefficients United State
  • Reconfigurable FIR Filter using CSD Coefficients United State
  • 2007
Hewlitt, “Canonical Signed Digit Representation for Fir Digital Filters
  • IEEE Workshop on Signal Processing Systems,
  • 2000