Area-Efficient VLSI Design of Reed–Solomon Decoder for 10GBase-LX4 Optical Communication Systems

@article{Hsu2004AreaEfficientVD,
  title={Area-Efficient VLSI Design of Reed–Solomon Decoder for 10GBase-LX4 Optical Communication Systems},
  author={Huai-Yi Hsu and An-Yeu Wu and Jih-Chiang Yeo},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2004},
  volume={53},
  pages={1245-1249}
}
The Reed-Solomon (RS) code is a widely used forward error correction technique to cope with the channel impairments in fiber communication systems. The typical parallel RS architecture requires huge hardware cost to achieve very high speed transmission data rate for optical systems. This brief presents an area-efficient VLSI architecture of the RS decoder by using a novel just-in-time folding modified Euclidean algorithm (JIT-FMEA). The JIT-FMEA VLSI architecture can greatly reduce the hardware… CONTINUE READING
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