Corpus ID: 14604271

Area Efficient Pipelined Architecture For Realization of FIR Filter Using Distributed Arithmetic

@inproceedings{SudhakarAreaEP,
  title={Area Efficient Pipelined Architecture For Realization of FIR Filter Using Distributed Arithmetic},
  author={V. Sudhakar and Nukala Suryanarayana Murthy and Lokam Anjaneyulu}
}
This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bitparallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter design. Pipelined DA architecture has achieved double the maximum frequency of operation when compared to their non-pipelined implementations with an increase in hardware. Filters… Expand

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Figure11: Simulation results for Q16.14 FIR filter Figure12: Simulation results for Q8.7 FIR filter
  • Figure11: Simulation results for Q16.14 FIR filter Figure12: Simulation results for Q8.7 FIR filter