Architectures for adaptive weight calculation on ASIC and FPGA

@article{Walke1999ArchitecturesFA,
  title={Architectures for adaptive weight calculation on ASIC and FPGA},
  author={R. Walke and R.W.M. Smith and Gordon Lightbody},
  journal={Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020)},
  year={1999},
  volume={2},
  pages={1375-1380 vol.2}
}
We compare two parallel array architectures for adaptive weight calculation based an QR-decomposition by Givens rotations. We present FPGA implementations of both architectures and compare them with an ASIC-based solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost are not critical. 
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