Architectures and synthesis algorithms for power-efficient businterfaces

@article{Benini2000ArchitecturesAS,
  title={Architectures and synthesis algorithms for power-efficient businterfaces},
  author={Luca Benini and Alberto Macii and Massimo Poncino and Riccardo Scarsi},
  journal={IEEE Trans. on CAD of Integrated Circuits and Systems},
  year={2000},
  volume={19},
  pages={969-980}
}
In this paper, we present algorithms for the synthesis of encoding and decoding interface logic that minimizes the average number of transitions on heavily-loaded global bus lines at no cost in communication throughput (i.e., one word is transmitted at each cycle). The distinguishing feature of our approach is that it does not rely on designer’s intuition, but it automatically constructs low-transition activity codes and hardware implementation of encoders and decoders, given information on… CONTINUE READING
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