Architecture of the Scalable Communications Core's Network on Chip

@article{Ilitzky2007ArchitectureOT,
  title={Architecture of the Scalable Communications Core's Network on Chip},
  author={David Arditti Ilitzky and Jeffrey D. Hoffman and Anthony Chun and Brando Perez Esparza},
  journal={IEEE Micro},
  year={2007},
  volume={27}
}
The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements. 

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