Architecture of a fast motion estimator for MPEG video coding


This paper describes the design of a high speed motion esfimator using the 2-0 log search algorifhm. The architecture consists of 5 simple processing elements (PE) where each PE is capable of computing the mrm-o$ absolute-dqference (SAD) to exploit the parallelism. For each step in the 2-0 log search procedure, the 5 SA Ds of fhe 5 search points are… (More)
DOI: 10.1109/ISPAN.1996.509028


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