Architecture design for deblocking filter in H.264/JVT/AVC

@inproceedings{Huang2003ArchitectureDF,
  title={Architecture design for deblocking filter in H.264/JVT/AVC},
  author={Yu-Wen Huang and To-Wei Chen and Bing-Yu Hsieh and Tu-Chih Wang and Te-Hao Chang and Liang-Gee Chen},
  booktitle={ICME},
  year={2003}
}
This paper,presents an efficient VLSI architecture for the dehlocking filter in H.ZWIVT/AVC. We use an array of 8x4 &bit shift registers with reconligurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation… CONTINUE READING
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