Architecture and Design of the MARS Hardware Accelerator

@article{Agrawal1987ArchitectureAD,
  title={Architecture and Design of the MARS Hardware Accelerator},
  author={Prathima Agrawal and William J. Dally and Ahmed K. Ezzat and W. C. Fischer and H. V. Jagadish and A. S. Krishnakumar},
  journal={24th ACM/IEEE Design Automation Conference},
  year={1987},
  pages={101-107}
}
MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event driven simulations of VLSI circuits. The highly pipelined and parallel architecture of MARS provides a performance comparable to existing hardware simulation engines while its highly flexible architecture supports a wide range of applications… CONTINUE READING