Architecture Design and Validation Methods


To tackle the exponential growth in the complexity of digital circuits, designers are moving to higher levels of abstraction in the design process. This chapter surveys the state of the art in modeling and synthesis techniques above RTL. The chapter focuses in three areas: Behavioral Synthesis, High-Level Control, and Data Flow. 
DOI: 10.1007/978-3-642-57199-2

Cite this paper

@inproceedings{Brger2000ArchitectureDA, title={Architecture Design and Validation Methods}, author={Egon B{\"o}rger}, booktitle={Springer Berlin Heidelberg}, year={2000} }