Architecture Description Languages

@inproceedings{Mishra2007ArchitectureDL,
  title={Architecture Description Languages},
  author={Prabhat Mishra and Nikil D. Dutt},
  year={2007}
}

Figures from this paper

A Study of Architecture Description Languages from a Model-based Perspective

  • W. QinS. Malik
  • Computer Science
    2005 Sixth International Workshop on Microprocessor Test and Verification
  • 2005
The operation state machine (OSM) model is discussed, the result of the first attempt to create high-level processor models and has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs.

Modeling and Specification of SoC Designs

This chapter introduces two of the most widely used system-level specifications: SystemC TLMs for hardware modeling, and UML activity diagrams for software modeling and presents how to extract formal models from these specifications.

An Architecture Description Language for Massively Parallel Processor Architectures

An architecture description language for modeling, simulation, and evaluation of massively parallel processor architectures that are designed for special purpose applications from the domain of embedded systems is introduced.

UML Component Diagram to Acme Compiler

This paper proposes an automatic mean to convert the popular UML component diagram represented by XMI into one of the formal architectural description languages called Acme, implemented using FLEX and YACC tools.

Early Verification of ISA Extension Specifications using Deep Reinforcement Learning

This paper proposes an early verification approach for ISE specifications and demonstrates the effectiveness of the approach for finding functional bugs in the executable specification of the ISE as well as specification gaps in theISE leading to information leakage.

Processeurs embarqués configurables pour la reproduction de tons

RESUME Les images a grande gamme dynamique (HDR) peuvent capturer les details d’une scene a la fois dans les zones les plus claires et les zones ombragees, en imitant les capacites du systeme visuel

User-defined Scenarios in Ubiquitous Environments: Creation, Execution Control and Sharing

A novel user-centric system called SaS for mobile personal devices that provides end-users with an easy access to services and a simple GUI to combine them into complex scenarios and proposes some mechanisms to maintain scenario availability in case of service/device unavailability.

References

SHOWING 1-10 OF 35 REFERENCES

A formal concurrency model based architecture description language for synthesis of software development tools

An MADL-based simulator synthesis framework is presented that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort and the efficacy of MADL as a practical and promising language for the development of programmable platforms is demonstrated.

Instruction set processor specifications (ISPS): The notation and its applications

  • M. Barbacci
  • Computer Science
    IEEE Transactions on Computers
  • 1981
The range of current and contemplated application areas are proof of the usefulness of the notation and its extension mechanisms, and the extension mechanisms which allow multiple applications or areas of research to co-exit and share machine descriptions are described.

Architecture Description Languages for Systems-on-Chip Design

A survey of recent use of Architecture Description Language (ADL) in the use of SOC architectures, and a discussion of several major challenges facing ADL-based codesign of future SOCs.

Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC]

This paper addresses automatic validation of processor, memory, and co-processor pipelines described in an ADL by presenting a graph-based modeling of architectures which captures both structure and behavior of the architecture.

RTL processor synthesis for architecture exploration and implementation

This paper presents a synthesis tool which preserves the full flexibility of the architecture description language LISA, while being able to generate the complete architecture on RT-level using systemC.

A survey of architecture description languages

  • P. Clements
  • Computer Science
    Proceedings of the 8th International Workshop on Software Specification and Design
  • 1996
A taxonomic survey of architecture description languages characterizes ADLs in terms of: the classes of systems they support; the inherent properties of the languages themselves; and the process and technology support they provide to represent, refine, analyze, and build systems from an architecture.

Retargetable compiled simulation of embedded processors using a machine description language

The article discusses the requirements of software development tools on processor models and presents the approach based on the LISA language, and the implementation of a retargetable environment consisting of compiled simulator, debugger, and assembler is presented.

A methodology for accurate performance evaluation in architecture exploration

A system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis.

EXPRESSION: a language for architecture exploration through compiler/simulator retargetability

EXPRESSION is described, a language supporting architectural design space exploration for embedded systems-on-chip (SOC) and automatic generation of a retargetable compiler/simulator toolkit and its efficacy in supporting exploration and automatic software toolkit generation for an embedded SOC codesign flow is demonstrated.

LISA-machine description language and generic machine model for HW/SW co-design

The development of a new language was necessary in order to cover the gap between coarse ISA models used in compilers, and instruction set simulators on the one hand, and detailed models used for hardware design on the other.