Architectural power analysis: The dual bit type method

  title={Architectural power analysis: The dual bit type method},
  author={Paul E. Landman and Jan M. Rabaey},
  journal={IEEE Trans. VLSI Syst.},
This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The Dual Bit Type (DBT) model, however, accounts not only for the random… CONTINUE READING
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  • Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gateor circuitlevel tools, but while other architecture-level techniques often err by 50-100% or more, the DBT method offers error rates on the order of 10-15%.


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Landman received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from the University of California, Berkeley

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