Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond

@inproceedings{Rose1997ArchitecturalAP,
  title={Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond},
  author={Jonathan Rose and Dwight D. Hill},
  booktitle={FPGA},
  year={1997}
}
Process technology advances tell us that the one-million gate Field-Programmable Gate Array (FPGA) will soon be here, and larger devices shortly after that. We feel that current architectures will not estend directly to this scale because: they do not handle routing delays effectively; they require excessive compile/place/route times; and because they do not exploit new opportunities are presented by the increase in available transistors and wiring. In this paper we describe several challenges… CONTINUE READING
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