Architectural-Level Fault Simulation Using Symbolic Data

  title={Architectural-Level Fault Simulation Using Symbolic Data},
  author={Jaushin Lee and Elizabeth M. Rudnick and Janak H. Patel},
Architectural-level circuit igormation has been utilized in hierarchical test generation and design for testabilit?; in recent years. Analysis at a high level makes a complete gate-level description of the circuit under test unnecessary. In this paper, we propose a new fault simulation technique which uses architectural-level information. This approach allows us to simulate stuck-at faults in specific modules within the context of the overall design. Gate-level descriptionr of all modules are… CONTINUE READING
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