Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array

  title={Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array},
  author={Frank Bouwens and Mladen Berekovic and Andreas Kanstein and Georgi Gaydadjiev},
Reconfigurable computational architectures are envisioned to deliver power efficient, high performance, flexible platforms for embedded systems design. The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer a tool flow to design sparsely interconnected 2D array processors with an arbitrary number of functional units, register files and interconnection topologies. This article presents an architectural… CONTINUE READING
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A Coarse-Grained Reconfigurable Architecture Template and its Compilation Techniques

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