Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link

@article{Raghavan2010ArchitecturalCO,
  title={Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link},
  author={Leneesh Raghavan and Ting Wu},
  journal={2010 23rd International Conference on VLSI Design},
  year={2010},
  pages={270-275}
}
To achieve high speed data signaling rates with the internal fast clock operating at half its speed,the XDR(extreme data rate) I/O link employs dual-edge signaling where in data bits are transmitted on both the edges(rise/fall) of transmit clock. Duty cycle correction technique is used to provide high frequency low jitter clocks that have 50% duty cycle. This paper compares two different techniques to implement duty cycle corrector(DCC). These techniquesare implemented in high speed I/O… CONTINUE READING