Architecting a reliable CMP switch architecture

  title={Architecting a reliable CMP switch architecture},
  author={Kypros Constantinides and Stephen M. Plaza and Jason A. Blome and Valeria Bertacco and Scott A. Mahlke and Todd M. Austin and Bin Zhang and Michael Orshansky},
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are addressed, computer vendors can expect low yields and short mean-times-to-failure. In this article, we examine the challenges of designing complex computing systems in the presence of transient and permanent faults. We select one small aspect of a typical… CONTINUE READING


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