Approximate logic synthesis for error tolerant applications

  title={Approximate logic synthesis for error tolerant applications},
  author={Doochul Shin and Sandeep K. Gupta},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
Error tolerance formally captures the notion that -- for a wide variety of applications including audio, video, graphics, and wireless communications -- a defective chip that produces erroneous values at its outputs may be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. All previous research on error tolerance has focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. In… CONTINUE READING
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  • Experiment results show that for an error rate threshold within 1%, our approach provides 9.43% literal reductions on average for all the benchmarks that we target.
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Publications referenced by this paper.

Approximate logic synthesis for error tolerant applications," Technical report, USC-CENG-2009-12

  • D. Shin, S. K. Gupta
  • University of Southern California,
  • 2009
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