Approximate SRAMs With Dynamic Energy-Quality Management

  title={Approximate SRAMs With Dynamic Energy-Quality Management},
  author={Fabio Frustaci and David Blaauw and Dennis Sylvester and Massimo Alioto},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
In this paper, approximate SRAMs are explored in the context of error-tolerant applications, in which energy is saved at the cost of the occurrence of read/write errors (i.e., signal quality degradation. [] Key Result Results show that the joint adoption of multiple bit-level techniques provides substantially larger energy gains than individual techniques.

Quality Aware Selective ECC for Approximate DRAM

This paper presents a technique that can be applied to approximate DRAMs under reduced refresh rate that allows to trim error rate at word-level, while still performing the refresh operation at the same rate for all cells.

Generalized Water-Filling for Source-Aware Energy-Efficient SRAMs

This work proposes a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems and shows that energy-optimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30 dB for an 8-bit accessed word.

An Emulator for Approximate Memory Platforms Based on QEmu

An emulation environment for approximate memory architectures, based on QEmu, which allows the execution of programs that can allocate some of their data in a memory zone subject to faults, and results that can be obtained by the emulator are presented.

CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation

CAST, a hardware/software approach to adjust the energy/quality of write operations in STT-MRAM caches in multicore systems based on the content of requested write operations, utilizes fine-grained cache-line-level actuation knobs with different levels of quality for individual write operations.

Quality Aware Approximate Memory in RISC-V Linux Kernel

This paper proposes and implements the management, in the Linux kernel, of multiple approximate memory banks, so that applications can then allocate approximate memory for their data structures selecting between different levels of approximation, depending on the requirements on output quality.

Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore’s Law

This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable circuits and systems, as promising direction to continue the historical exponential energy downscaling

Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation

An innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to state-of-the-art truncation schemes, which translates into energy reduction at a given quality target.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

A progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays is proposed, by which the power consumption is reduced at the expense of small quality degradation.

Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations.

SRAM Bit-line Swings Optimization using Generalized Waterfilling

Numerical results show that energy-optimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word.



SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

A voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need and two variation-resilient techniques are selectively applied to bit positions having larger impact on the overall quality.

13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS

Voltage scaling is widely used to improve SRAM energy efficiency, but the resulting energy benefits are limited by the minimum voltage ensuring error-free operation, Vmin, which has stagnated due to growing process variation in advanced technology nodes.

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode, which leads to higher dynamic energy consumption than the conventional approach.

Adaptive Cache Design to Enable Reliable Low-Voltage Operation

This paper proposes an adaptive cache design that enables the operating system to optimize for performance or energy efficiency without sacrificing reliability, and proposed mechanism enables a cache with a wide operating range, where the cache can use a variable part of its data array to store error-correcting codes.

Designing a processor from the ground up to allow voltage/reliability tradeoffs

Current processor designs have a critical operating point that sets a hard limit on voltage scaling. Any scaling beyond the critical voltage results in exceeding the maximum allowable error rate,

Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications

A heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stores in the smaller ones, which allows the better video quality even in lower voltage operation.

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

  • H. PiloC. Adams M. I. Younus
  • Engineering
    2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
This work describes an SRAM that is optimized for leakage and performance as top priorities over density and features a new bitcell implemented with a fine-granularity power-gating technique to reduce BC leakage.

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

We present a voltage-scalable and process-variation resilient, hybrid memory architecture, suitable for use in MPEG-4 video processors such that power dissipation can be traded for graceful

Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology

A new design of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology achieves a maximum leakage up to 85% lower without paying significant delay penalties.

Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications

An ultra-low voltage split-data-aware 10T and 8T (SDA-10T-8T) embedded static random access memory (SRAM) design for MPEG-4 video processors that can achieve a 95% reduction in active power, with no significant degradation in frame quality.