Application-specific array processors for binary prefix sum computation

Abstract

The main contribution of this work is to propose two application-specific bus architectures for computing the p r e f i sums of a binary sequence. Our architectures feature the following characteristics: (1) all broadcasts occur on buses of length I5 or 63; ( 2 ) we use a new technique t h a ~ we call shift switching which allows switches to cyclically… (More)
DOI: 10.1109/SPDP.1994.346174

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