Applicability of dual layer metal nanocrystal flash memory for NAND 2 or 3-bit/cell operation: Understanding the anomalous breakdown and optimization of P/E conditions


Large memory window (6–9V) program/erase (P/E) cycling endurance is studied for evaluating their suitability for MLC operation. Effect of NC area coverage and device size is evaluated using statistical method. Constant voltage stress (CVS) measurements and 2-D simulations are extensively used to evaluate the impact of carrier; type, fluence, and… (More)


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