Anomalous Behavior of Synchronizer and Arbiter Circuits

  title={Anomalous Behavior of Synchronizer and Arbiter Circuits},
  author={Thomas J. Chaney and Charles E. Molnar},
  journal={IEEE Transactions on Computers},
Observations are shown of oscillatory and metastable behavior of flip-flops in response to logically undefined input conditions such as those that occur in synchronizers and arbiters. Significant systems failures have resulted from this fundamentally inescapable problem that is generally not appreciated by system designers and users. 
The Anomalous Behavior of Flip-Flops in Synchronizer Circuits
It is found that the obtained results are in good correlation with observed failure rates of a synchronizer with both short and long flip-flop resolution times allowed. Expand
Simulating Improbable Events
A novel simulation technique is presented that allows for accurate waveforms for the metastability failures and similar events in circuits such as flip-flops, sense amplifiers and synchronizers. Expand
Metastability and Synchronizers: A Tutorial
  • R. Ginosar
  • Computer Science
  • IEEE Design & Test of Computers
  • 2011
This tutorial provides a glimpse into the theory and practice of metastability, which can arise whenever a signal is sampled close to a transition, leading to indecision as to its correct value. Expand
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  • Computer Science
  • Electron. Notes Theor. Comput. Sci.
  • 2009
Simple models of metastability have served us well up to now, but more recently work on the characterisation of deep metastability has demonstrated effects in commonly used components that may need to be taken into account. Expand
Metastable States in Asynchronous Digital Systems: Avoidable or Unavoidable?
Abstract The synchronization of asynchronous signals can lead to metastable behavior and malfunction of digital circuits. It is believed - but not proven - that metastability principally cannot beExpand
Metastable Behavior in Digital Systems
A number of techniques are described and evaluated for reducing the probability of metastable failure in fault-free digital circuits when asynchronous inputs have critical timing combinations that result in metastable operation. Expand
An Experimental Study of Metastability-Induced Glitching Behavior
The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount, however, the manifestation of metastable properties at a flip-flop outpacing the efforts to address these challenges is surprising. Expand
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This paper addresses a novel priority arbiter architecture to solve the metastability problem and shows that this new design has better immunity against metastable operation. Expand
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The interaction problem between asynchronous logic elements is formulated with emphasis on the synchronizer and the principle result is to predict, in a probabilistic manner, the time necessary to move from the metastable point to one of the stable boundaries. Expand


Time Loss Through Gating of Asynchronous Logic Signal Pulses
  • I. Catt
  • Computer Science
  • IEEE Trans. Electron. Comput.
  • 1966
The gating of asynchronous signals causes logical errors. It is possible to reduce the frequency of these errors, but the price paid is a severe loss of time and extra cost in hardware.