Analyzing the Issues of Soft Error Rates(SER)in Technology Trend & Reliability for CMOS designs

  • Sirisha . Gadiparti
  • Published 2015

Abstract

Soft error rate (SER) has become a critical reliability issue for CMOS designs due to continuous technology scaling. However, the striking-time and multi-cycle effects have not been properly considered in SER for advanced CMOS designs. So this paper, reviews the striking-time and multicycle effects are formulated into the problem of SER estimation. Also this paper reviews impact of new microprocessor technology on microprocessor soft error rate (SER). As microprocessor feature sizes decreased from 180nm to 65nm, memory error rates per bit decreased, but our data indicates a reversal of this trend at 40nm. SER as a function of power supply voltage (Vdd) over a range of 1.2V down to 0.5V, and the data shows SER significantly increases as Vdd decreases. This result implies that dynamic voltage frequency scaling (DVFS), a commonly used microprocessor energy reduction technique, could cause a significant decrease in microprocessor reliability. The data also show that more energy-efficient transistors using back bias technique do not appear to significantly impact microprocessor

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Cite this paper

@inproceedings{Gadiparti2015AnalyzingTI, title={Analyzing the Issues of Soft Error Rates(SER)in Technology Trend & Reliability for CMOS designs}, author={Sirisha . Gadiparti}, year={2015} }