Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area

Abstract

The increasing power consumption of processors has made power reduction a first-order priority in processor design. Voltage scaling is one of the most powerful power-reduction techniques introduced to date, but is limited to some minimum voltage VDDMIN. Below VDDMIN on-chip SRAM cells cannot all operate reliably due to increased process variability with… (More)
DOI: 10.1109/TVLSI.2011.2173220

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