Analytical thermal model for multilevel VLSI interconnects incorporating via effect

  title={Analytical thermal model for multilevel VLSI interconnects incorporating via effect},
  author={Ting-Yen Chiang and Krishnadas Banerjee and K. C. Saraswat},
  journal={IEEE Electron Device Letters},
The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k/sub ILD,eff/, with k/sub ILD/,/sub eff/=k/sub ILD//spl eta//, where /spl eta/ is a physical correction factor, with 0</spl eta/<1. Both the spatial temperature profile along the metal lines… CONTINUE READING
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