Analytical Model for the Propagation Delay of Through Silicon Vias

@article{Khalil2008AnalyticalMF,
  title={Analytical Model for the Propagation Delay of Through Silicon Vias},
  author={DiaaEldin Khalil and Yehea I. Ismail and Muhammad M. Khellah and Tanay Karnik and Vivek De},
  journal={9th International Symposium on Quality Electronic Design (isqed 2008)},
  year={2008},
  pages={553-556}
}
This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed. The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy… CONTINUE READING
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Electrical characterization of through - wafer interconnects , " in

  • S. M. Donovan T. E. Lawrence, W. B. Knowlton, J. Rush-Byers, A. J. Moll
  • Proc . of IEEE Workshop on Microelectronics and…
  • 2004

Opportunities for Reduced Power Dissipation Using Three-Dimensional Integration

  • J. Joyner, J. Meindl
  • in Proc. of IEEE International Interconnect…
  • 2002

Electrical through-wafer interconnects with sub-pico farad parasitic capacitance

  • C. H. Cheng, A. S. Ergun, B. T. Khuri-Yakub
  • Proc. of Microelectromechanical Systems…
  • 2001
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