Analytical Model and Optimization for Variable Drift Region Width SOI LDMOS Device

@article{Wang2016AnalyticalMA,
  title={Analytical Model and Optimization for Variable Drift Region Width SOI LDMOS Device},
  author={Ying Wang and Xiong-Fei Meng and Pan-Pan Tang and Su-Fen Cui},
  journal={IEEE Transactions on Electron Devices},
  year={2016},
  volume={63},
  pages={4352-4358}
}
In this paper, we propose an analytical model for the variable drift region width (VDRW) silicon-on-insulator lateral double-diffused MOS (SOI LDMOS) device. Using the proposed model, for example, the breakdown voltage 375 V of VDRW SOI LDMOS is obtained with a 18-μm drift region length, while the average value of the surface electric field can reach 20.8 V/μm. A 3-D device simulator, Sentaurus, is used to investigate the performance of the VDRW structure. By analyzing the simulation results… CONTINUE READING

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