Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers

@article{Casha2009AnalysisOT,
  title={Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers},
  author={Owen Casha and Ivan Grech and Franck Badets and Dominique Morche and Joseph Micallef},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2009},
  volume={56},
  pages={132-136}
}
A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and… CONTINUE READING

From This Paper

Figures, tables, and topics from this paper.

References

Publications referenced by this paper.
Showing 1-10 of 11 references

An 800 MHz - 122 dBc / Hz - at - 200 kHz clock multiplier based on a combination of PLL and recirculating DLL , ” in

  • W. Dally R. F. Rad, H. T. Ng, R. Senthinathan, M. J. E. Lee, R. Rathi, J. Poulton
  • Proc . IEEE Int . Solid - State Circuits Conf .
  • 2008

Density of the ratio of two normal random variables and applications

  • T. P. Gia, N. Turkkan, E. Marchand
  • Commun. Stat., Theory Methods, vol. 35, no. 7–9…
  • 2006
1 Excerpt

A -107 dBc 10 kHz carrier offset 2-GHz DLL-based frequency synthesizer

  • J. Zhuang, Q. Du, T. Kwasniewski
  • Proc. IEEE Custom Integr. Circuits Conf., , pp…
  • 2003
3 Excerpts