Analysis of subthreshold leakage reduction in CMOS digital circuits

@article{Deepaksubramanyan2007AnalysisOS,
  title={Analysis of subthreshold leakage reduction in CMOS digital circuits},
  author={B. S. Deepaksubramanyan and Adrian Nunez},
  journal={2007 50th Midwest Symposium on Circuits and Systems},
  year={2007},
  pages={1400-1404}
}
Leakage power dissipation is projected to grow exponentially in the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices such as cellular phones and PDAs since they have long idle times. Several techniques have been proposed that efficiently minimize this leakage power loss. A comprehensive survey and analysis of various subthreshold leakage power reduction techniques that are applicable to current… CONTINUE READING
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