Analysis of microbump induced stress effects in 3D stacked IC technologies

@article{Ivankovic2011AnalysisOM,
  title={Analysis of microbump induced stress effects in 3D stacked IC technologies},
  author={Andrej Ivankovic and Geert Van der Plas and V. Moroz and M. Choi and Vladimir Cherman and Abdelkarim Mercha and Paul Marchal and Marcel Gonzalez and Geert Eneman and W. Zhang and Thibault Buisson and Mikael Detalle and Antonio La Manna and Diederik Verkest and Gerald Beyer and Eric Beyne and Bart Vandevelde and Ingrid De Wolf and Dirk Vandepitte},
  journal={2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International},
  year={2011},
  pages={1-5}
}
Besides the stress around Cu TSV's, also the stress induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating stress have to be addressed. Therefore, this work quantifies the stress and its effects associated with Cu microbumps and their interaction with underfill material in 3D stacks by using a combined experimental and theoretical approach. We report on the stress generated by backside microbumps affecting… CONTINUE READING