## An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs

- Shao Jie, Ye Ning, Zhang Xiao-Yan
- 2008 International Conference on Computer Scienceâ€¦
- 2008

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@article{Govindu2004AnalysisOH, title={Analysis of high-performance floating-point arithmetic on FPGAs}, author={Gokul Govindu and Ling Zhuo and Seonil B. Choi and Viktor K. Prasanna}, journal={18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.}, year={2004}, pages={149-} }

- Published 2004 in 18th International Parallel and Distributedâ€¦
DOI:10.1109/IPDPS.2004.1303135

Summary form only given. FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. We analyze the floating-point multiplier and adder/subtractor units by considering the number of pipeline stages of the units as a parameter and use throughput/area as the metric. Weâ€¦Â CONTINUE READING

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