Analysis of forward error correction methods for nanoscale networks-on-chip

  title={Analysis of forward error correction methods for nanoscale networks-on-chip},
  author={T. Lehtonen and P. Liljeberg and J. Plosila},
The amount of errors in future nanoscale technologies is expected to increase dramatically when compared to technologies that have line width larger than 90 nm. In nanoscale CMOS circuits fault tolerance is one of the most important design constraints to sustain system reliability at an acceptable level. We analyze different error correcting coding methods for on-chip communication networks of future nanoscale multiprocessor systems. The implemented communication circuits are compared in terms… Expand
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