Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine
Modern-day microprocessors use variants on Tomasulo’s Algorithm, a dynamic scheduling algorithm, for instruction-level hardware parallelism. This parallelism is accomplished by processing instructions in several Functional Units (FUs) simultaneously. Described is an approach to extend this algorithm to utilize an array of reconfigurable FUs by tracking pipeline stalls and FU usage. To analyze this approach, presented is a comparison of simulated systems with unbounded FUs, a fixed FU set similar to a modern processor, a hybrid fixed/variable set of FUs, and a completely variable set of FUs. Initial results for a simple test program indicate that such a reconfigurable-FU machine offers marginal performance benefits of 9.5-14.9%.