Analysis of Specified Bit Handling Capability of Combinational Expander Networks

@article{Jas2007AnalysisOS,
  title={Analysis of Specified Bit Handling Capability of Combinational Expander Networks},
  author={Abhijit Jas and Srinivas Patil},
  journal={22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)},
  year={2007},
  pages={252-260}
}
Test compression schemes based on combinational expander networks have become very popular in recent times. The idea behind these schemes is to use m bits from the tester to produce N(m < N) bits for the internal scan chains of the circuit under test. In this paper we address the general problem of designing combinational expander networks with N outputs which guarantee that any S specified bits can be justified at the expander output. By analyzing the constraints imposed on the output space of… CONTINUE READING

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  • M. A. Shah, J. H. Patel, J. Rearick
  • Proc. IEEE CS Annual Symposium on VLSI,
  • 2004
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